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dual differential 16 - bit, 1 msps pulsar adc 12 .0 mw in q sop data sheet AD7903 features 1 6 - bit resolution with no missing codes throughput: 1 msps low power dissipation 7.0 mw at 1 msps (v dd1 and v dd2 only ) 1 2 .0 mw at 1 msps (t otal) 140 w at 10 ksps inl: 0.5 lsb typical, 2.0 lsb maximum sinad: 93.5 db at 1 khz thd: ?112 db at 1 khz true differential analog input range: v ref 0 v to v ref with v ref between 2.4 v to 5.1 v a llows use of a ny input range easy to drive with the ada4941 - 1 no pipeline delay single - supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial port interface ( spi ) /qspi/microwire/dsp compatible 2 0 - lead qsop package wide operating temp erature range: ?40c to +125c applications battery - powered equipment communications automated test equipment ( ate ) data acquisition medical instrumentation redundant measurement simultaneous s ampling general description the AD7903 is a dual 1 6 - bit, successive approximation, analog - to - digital converter (adc) that operates from a single power supply, vdd x, per adc . it contains two low power, high speed, 1 6 - bit sampling a dc s and a versatile serial port interface (spi) . on the cnv x rising edge, the AD7903 samples the voltage difference between the in x + and in x ? pins. the voltages on these pins usually swing in oppo site phase s between 0 v and v ref . the externally applied reference voltage of the ref x pins ( v ref ) can be set independent ly from the supply voltage pins , vdd x . the power of the device scales linearly with throughput. u sing the sdi x input s, t he spi - compatible serial interface can also daisy - chain multiple adcs on a single 3 - wire bus and provide an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio x supplies . the AD7903 is available in a 2 0 - lead q sop package with operation specified from ? 4 0c to + 125 c. table 1 . msop 14 - /16 - /18 - bit pulsar ? adc s bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18 ad7691 1 ad7690 1 ad7982 1 ada4941 - 1 ada4841 - x 16 ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941 - 1 ad7683 ad7687 1 ad7688 1 AD7903 ada4841 - x ad7684 ad7694 ad7693 1 ad7902 14 ad7940 ad7942 1 ad7946 1 1 pin - for - pin compatible. function al block diagram figure 1. gnd vdd1 vdd2 2.5v ref1 ref2 ref = 2.5v to 5v adc1 in1+ in1? vio1 sdi1 sck1 cnv1 sdo1 vio1/vio2 sdi1/sdi2 sck1/sck2 cnv1/cnv2 sdo1 ref 10v, 5v, ... adc2 in2+ in2? vio2 sdi2 sck2 cnv2 sdo2 sdo2 ref 10v, 5v, ... 3-wire or 4-wire interface (spi, cs, and chain modes) AD7903 ada4941-1 ada4941-1 11755-001 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
AD7903* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? AD7903 evaluation board documentation application notes ? an-742: frequency domain response of switched- capacitor adcs ? an-931: understanding pulsar adc support circuitry ? an-935: designing an adc transformer-coupled front end data sheet ? AD7903: dual differential 16-bit, 1 msps pulsar adc 12.0 mw in qsop data sheet product highlight ? [no title found] product highlight ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-609: evaluating the AD7903 dual differential, 16-bit, 1 msps pulsar adc tools and simulations ? AD7903 ibis model reference designs ? cn0374 reference materials press ? analog devices releases two dual a/d converters with lowest power/highest linearity combination available product selection guide ? sar adc & driver quick-match guide technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc tutorials ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" design resources ? AD7903 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD7903 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD7903 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 13 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 typical connection diagram .................................................... 15 analog inputs .............................................................................. 15 driver amplifier choice ........................................................... 16 single - to - differential driver .................................................... 16 voltage reference input ............................................................ 17 power supply ............................................................................... 17 digital interface .......................................................................... 17 cs mode ...................................................................................... 18 chain mode ................................................................................ 22 applications information .............................................................. 24 simultaneous sampling ............................................................. 24 functi onal safety considerations ............................................ 25 layout ............................................................................................... 26 evaluating performance of the AD7903 .................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 8/14 rev. a to rev. b changed standby current unit from na to a ........................... 4 changes to power supply section ................................................ 1 7 1/14 rev. 0 to rev. a change to gain error temperature drift parameter .................. 3 changes to figure 12 ........................................................................ 9 changes to figure 17 and figure 20............................................. 10 changes to figure 28 ...................................................................... 11 12 /13 revision 0: initial version rev. b | page 2 of 28
data sheet AD7903 specifications v dd = 2.5 v, v io = 2.3 v to 5.5 v, v ref = 5 v, t a = ? 40c to +125c, unless otherwise noted. 1 table 2 . parameter test conditions /comments min typ max unit resolution 16 bits analog input voltage range in x + ? in x? ? v ref +v ref v absolute input voltage in x +, in x? ? 0.1 v ref + 0.1 v common - mode input range in x +, in x? v ref 0.475 v ref 0.5 v ref 0.525 v analog input cmrr f in = 450 khz 67 db leakage current at 25c acquisition phase 200 na input impedance see the analog input s section accuracy no missing codes 16 bits differential nonl inearity error v ref = 5 v ? 1.0 0.4 +1.0 lsb 2 v ref = 2.5 v 0.7 lsb 2 integral nonl inearity error v ref = 5 v ? 2.0 0 .5 + 2.0 lsb 2 v ref = 2.5 v 0.4 lsb 2 transition noise v ref = 5 v 0.75 lsb 2 v ref = 2.5 v 1.2 lsb 2 gain error 3 t min to t max ? 0.0 4 0.006 +0.0 4 % fs gain error temperature drift 0.19 ppm/c gain error match 3 t min to t max 0.0 0.0 25 % fs offset error 3 t min to t max ? 0.5 0.015 +0.5 mv offset temperature drift 0.3 ppm/c offset error match 3 t min to t max 0.05 1. 0 mv power supply sensitivity v dd = 2.5 v 5% 0.1 lsb 2 throughput conversion rate v io 2.3 v up to 85c, v io 3.3 v above 85c , up to 125c 0 1 msps transient response full - scale step 290 ns ac accuracy dynamic range v ref = 5 v 9 5 .5 db 4 v ref = 2.5 v 9 2 .5 db 4 over s ampled dynamic range f o ut = 10 ksps 11 3.5 db 4 signal - to - noise ratio ( snr ) f in = 1 khz, v ref = 5 v 92 94 db 4 f in = 1 khz, v ref = 2.5 v 8 9 91 db 4 spurious - free dynamic range ( sfdr ) f in = 1 khz ? 115 db 4 total harmonic distortion ( thd ) f in = 1 khz ? 112 db 4 signal - to - (noise + distortion) ( sinad ) f in = 1 khz, v ref = 5 v 91.5 93.5 db 4 f in = 1 khz, v ref = 2.5 v 8 8.5 90.5 db 4 channel -to - channel isolation f in = 10 khz ? 120 db 4 1 in this data sheet, the voltages for the vddx, viox, and refx pins are indicated by v dd , v io , and v ref , respectively. 2 with the 5 v input range, 1 lsb = 152.6 v. with the 2. 5 v input range, 1 lsb = 76.3 v . 3 see the terminology section. these specifications include full temperature range variation , but they do not include the error contribution from the ex ternal reference. 4 all specifications in decibels (db) are referred to a full - scale input fsr. although these parameters are referred to full scale, they are tested with an input signal at 0.5 db below full scale, unless otherwise specified. rev. b | page 3 of 28
AD7903 data sheet v dd = 2.5 v, v io = 2.3 v to 5.5 v, t a = ? 40c to +125c, unless otherwise noted. 1 table 3 . parameter test conditions /comments min typ max unit reference voltage range 2.4 5.1 v load current 1 msps, v ref = 5 v , e ach adc 330 a sampling dynamics ? 3 db input bandwidth 10 mhz aperture delay v dd = 2.5 v 2.0 ns aperture delay match v dd = 2.5 v 2.0 ns digital inputs logic levels v il v io > 3 v ? 0.3 + 0.3 v io v v io 3 v ? 0.3 + 0.1 v vio v v ih v io > 3 v 0.7 v io v io + 0.3 v v io 3 v 0.9 v io v io + 0.3 v i il ? 1 +1 a i ih ? 1 +1 a digital outputs data format twos complement bits pipeline delay no delay; conversion results available immediately after conversion is complete 0 samples v ol i sink = + 500 a 0.4 v v oh i source = ?500 a v io ? 0.3 v power supplies vdd x 2.375 2.5 2.625 v vio x specified performance 2.3 5.5 v viox range full range 1.8 5.5 v i vddx each adc 1.4 1.6 ma i viox each adc 0.2 0.45 ma standby current 2 , 3 v dd and v io = 2.5 v, 25c 0.35 a power dissipation 10 ksps throughput 140 w 1 msps throughput 12.0 16 mw vdd only 7.0 mw ref only 3.3 mw vio only 1.7 mw energy per conversion 7.0 nj/sample temperature range 4 specified performance t min to t max ? 40 +125 c 1 in this data sheet, the voltages for the vddx, viox, and refx pins are indicated by v dd , v io , and v ref , respectively. 2 with all digital inputs forced to vio x or to ground as required. 3 during the acquisition phase. 4 contact analog devices, inc. , for the extended temperature range. rev. b | page 4 of 28
data sheet AD7903 rev. b | page 5 of 28 timing specifications ?40c to +125c, v dd = 2.37 v to 2.63 v, v io = 2.3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load conditions. table 4. parameter symbol min typ max unit conversion time (cnvx rising edge to data available) t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc viox above 2.3 v 1000 ns cnvx pulse width (cs mode) t cnvh 10 ns sckx period (cs mode) t sck viox above 4.5 v 10.5 ns viox above 3 v 12 ns viox above 2.7 v 13 ns viox above 2.3 v 15 ns sckx period (chain mode) t sck viox above 4.5 v 11.5 ns viox above 3 v 13 ns viox above 2.7 v 14 ns viox above 2.3 v 16 ns sckx low time t sckl 4.5 ns sckx high time t sckh 4.5 ns sckx falling edge to data remains valid t hsdo 3 ns sckx falling edge to data valid delay t dsdo viox above 4.5 v 9.5 ns viox above 3 v 11 ns viox above 2.7 v 12 ns viox above 2.3 v 14 ns cnvx or sdix low to sdox, d15 (msb) valid (cs mode) t en viox above 3 v 10 ns viox above 2.3 v 15 ns cnvx or sdix high or last sckx falling edge to sdox high impedance (cs mode) t dis 20 ns sdix valid setup time from cnvx rising edge (cs mode) t ssdicnv 5 ns sdix valid hold time from cnvx rising edge (cs mode) t hsdicnv 2 ns sckx valid setup time from cnvx rising edge (chain mode) t ssckcnv 5 ns sckx valid hold time from cnvx rising edge (chain mode) t hsckcnv 5 ns sdix valid setup time from sckx falling edge (chain mode) t ssdisck 2 ns sdix valid hold time from sckx falling edge (chain mode) t hsdisck 3 ns sdix high to sdox high (chain mode with busy indicator) t dsdosdi 15 ns figure 2. load circuit for digital interface timing figure 3. voltage levels for timing 500a i ol 500a i oh 1.4v to sdox c l 20pf 11755-002 x% viox 1 y% viox 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for viox 3.0v, x = 90 and y = 10; for viox > 3.0v, x = 70 and y = 30. 2 minimum v ih and maximum v il used. see specifications for digital inputs parameter in table 3. 11755-003
AD7903 data sheet rev. b | page 6 of 28 absolute maximum ratings table 5. parameter rating analog inputs inx+, inx? to gnd 1 ?0.3 v to v ref + 0.3 v or 10 ma supply voltage refx, viox to gnd ?0.3 v to +6.0 v vddx to gnd ?0.3 v to +3.0 v vddx to viox +3 v to ?6 v digital inputs to gnd ?0.3 v to v io + 0.3 v digital outputs to gnd ?0.3 v to v io + 0.3 v storage temperature range ?65c to +150c junction temperature 150c lead temperatures vapor phase (60 sec) 255c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 see the analog inputs section for an explanation of inx+ and inx?.
data sheet AD7903 rev. b | page 7 of 28 pin configuration and fu nction descriptions figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1, 6 ref1, ref2 ai reference input voltage. the refx range is 2.4 v to 5.1 v. these pins are referred to the gnd pin, and decouple each pin closely to the gnd pin with a 10 f capacitor. 2, 7 vdd1, vdd2 p power supplies. 3, 8 in1+, in2+ ai differential positive analog inputs. 4, 9 in1?, in2? ai differenti al negative analog inputs. 5, 10 gnd p power supply ground. 11, 16 cnv2, cnv1 di conversion inputs. these inputs have multiple functi ons. on the leading edge, they initiate conversions and select the interface mode of the device: chain mode or active low chip select (cs ) mode. in cs mode, the sdox pins are enabled when the cnvx pins are low. in chain mode, the data must be read when the cnvx pins are high. 12, 17 sdo2, sdo1 do serial data outputs. the conversion result is output on these pins. the conversion result is synchronized to sckx. 13, 18 sck2, sck1 di serial data clock inputs. when the device is selected, the conversion results are shifted out by these clo cks. 14, 19 sdi2, sdi1 di serial data inputs. these inputs prov ide multiple functions. they select the interface mode of the adc, as follows: cs mode is selected if the sdix pins are high during the cnvx rising edge. in this mode, either sdix or cnvx can enable the serial output signals when low. if sdix or cnvx is low when the conversion is complete, the busy indicator feature is enabled. 15, 20 vio2, vio1 p input/output interface digital power. nominally at the same supply as the host interface (2.5 v or 3.3 v). 1 ai = analog input, di = digital input, do = digital output, and p = power. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdd1 in1+ in1? vdd2 ref2 gnd ref1 sdi1 sck1 sdo1 sdi2 vio2 cnv1 gnd in2? in2+ cnv2 sdo2 sck2 vio1 AD7903 top view (not to scale) 11755-004
AD7903 data sheet typical performance characteristics v dd = 2.5 v, v ref = 5.0 v, v io = 3.3 v, t a = 25c , f sample = 1 msps, unless otherwise noted. figure 5 . integral nonlinearity vs. code, v ref = 5 v figure 6 . integral nonlinearity vs. code, v ref = 2.5 v figure 7 . fft plot, v ref = 5 v figure 8 . differential nonlinearity vs. code, v ref = 5 v figure 9 . differential nonlinearity vs. code, v ref = 2.5 v figure 10 . fft plot, v ref = 2.5 v 0 6553 6 1638 4 3276 8 4915 2 1 . 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 i n l ( l s b ) c o d e 1 1755 - 40 5 p o s i t i ve i n l : + 0 . 35 l sb n e g a t i ve i n l : ?0 . 39 l sb 0 6553 6 1638 4 3276 8 4915 2 p o s i t i ve i n l : + 0 . 39 l sb n e g a t i ve i n l : ?0 . 44 l sb 1 . 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 i n l ( l s b ) c o d e 1 1755 - 40 6 0 500 100 200 300 400 11755-407 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr (db) frequency (khz) f sample = 1msps f in = 10khz snr = 95.04db thd = ?117.3db sfdr = 114.6db sinad = 95.02db 1 . 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 dn l ( l s b ) c o d e 1 1755 - 40 8 0 6553 6 1638 4 3276 8 4915 2 p o s i t i ve dn l : + 0 . 31 l sb n e g a t i ve dn l : ?0 . 38 l sb 1 . 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0 . 2 0 . 4 0 . 6 0 . 8 dn l ( l s b ) c o d e 1 1755 - 40 9 0 6553 6 1638 4 3276 8 4915 2 p o s i t i ve dn l : + 0 . 39 l sb n e g a t i ve dn l : ?0 . 39 l sb 11755-410 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr (db) frequency (khz) f sample = 1msps f in = 10khz snr = 91.96db thd = ?110.2db sfdr = 114.5db sinad = 91.91db 0 500 100 200 300 400 rev. b | page 8 of 28
data sheet AD7903 figure 11 . histogram of a dc input at the code center, v ref = 5 v figure 12 . histogram of a dc input at the code transition, v ref = 5 v figure 13 . snr, sinad, and enob vs. reference voltage figure 14 . histogram of a dc input at the code center, v ref = 2.5 v figure 15 . snr vs. input level figure 16 . thd, sfdr vs. reference voltage 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 ffe1 ffe2 ffe3 ffe4 ffe5 ffe6 ffe7 ffe8 ffe9 ffea number of occurrences codes in hex 1 1755-4 1 1 40000 35000 30000 25000 20000 15000 10000 5000 0 ffd2 ffd3 ffd4 ffd5 ffd6 ffd7 ffd8 ffd9 ffda ffdb number of occurrences codes in hex 1 1755-412 100 98 96 94 92 90 88 86 84 82 80 16.0 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 snr, sinad (db) enob (bits) reference voltage (v) snr sinad enob 1 1755-413 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 fff1 fff2 fff3 fff4 fff5 fff6 fff7 fff8 fff9 fffb fffa number of occurrences codes in hex 1 1755-414 98 97 96 95 94 93 92 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 snr (db) input level (db) 1 1755-415 ?95 ?125 ?110 ?115 ?105 ?100 ?120 115 85 100 95 105 110 90 2.25 5.25 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr 1 1755-416 rev. b | page 9 of 28
AD7903 data sheet figure 17 . sinad vs. input frequency figure 18 . snr vs. temperature figure 19 . operating currents of each adc vs. vdd supply voltage figure 20 . thd v s. input frequency figure 21 . thd vs. temperature fiure eratin currents of ach c s sae atecr 96 85 86 87 88 89 90 91 92 93 94 95 10 input frequency (khz) sinad (db) 100 1 1755-417 94.8 93.4 93.6 93.8 94.0 94.2 94.4 94.6 temperature (c) snr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-418 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) 2.425 2.475 vdd voltage (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio 11755-050 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 10 input frequency (khz) thd (db) 100 1 1755-420 ?100 ?105 ?110 ?115 ?120 ?125 temperature (c) thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-421 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 100 sample rate (ksps) current (ma) 1000 i vdd i vio t a = 25c 1 1755-422 rev. b | page 10 of 28
data sheet AD7903 figure 23 . operating currents of each adc vs. temperature figure 24 . offset error vs. temperature fiure ain rror s teerature fiure owe r - own current of ach c s teerature fiure ffset rror match s teerature fiure ain rror match s teerature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd i ref i vio 11755-053 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 temperature (c) offset error (mv) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-424 0.05 ?0.05 ?0.03 ?0.01 0.01 0.03 temperature (c) gain error (% fs) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-425 8 7 6 5 4 3 2 1 0 current (a) ?55 ?35 ?15 5 25 temper a ture (c) 45 65 85 105 125 i vdd + i vio 11755-054 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 temperature (c) offset error match (mv) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-427 0.010 ?0.010 ?0.005 0 0.005 temperature (c) gain error match (% fs) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1755-428 rev. b | page 11 of 28
AD7903 data sheet figure 29 . channel - to - ch annel isolation vs. temperature figure 30 . channel - to - channel isolation vs. input frequency ?11 2 ?11 3 ?11 4 ?11 5 ?11 6 ?11 7 ?11 8 ?11 9 ?12 0 ?12 1 t empera t ur e ( c ) ?5 5 ?3 5 ?1 5 5 2 5 4 5 6 5 8 5 10 5 12 5 f i n = 10k h z f s a m p l e = 1 msps 1 1755 - 429 chann el -t o -chann el i so l a t io n (d b ) ?112 ?124 ?122 ?120 ?118 ?116 ?114 10 input frequency (mhz) channel-to-channel isolation (db) 100 1 1755-430 rev. b | page 12 of 28
data sheet AD7903 terminology integral nonlinearity error (inl) i nl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb b eyond the last code transition. the deviation is measured from the middle of each code to the true straight. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error offset error is the difference bet ween the ideal midscale voltage (that is, 0 v) and the actual voltage pro ducing the midscale output code ( that is, 0 lsb ) . offs et error match it is the difference in offsets, expressed in millivolts between the channels of a multichannel converter. it is computed with the following equation: offset matching = voffset max ? voffset min where: voffset max is the most positive offset error. voffset min is the most negative offset error. offset matching is usually expressed in millivolts with the full - scale input range stated in the product data sheet. gain error the first transition (from 100 00 to 100 01) should occur at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) occur s for an analog voltage that is 1? lsb below the nominal full scale (4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. gain error match it is the ratio of the maximum full scale to the m inimum full scale of a multichannel adc. it is expressed as a percentage of full scale using the following equation: % 100 2 ? ? ? ? ? ? ? ? ? ? ? ? + ? = min max min max fsr fsr fsr fsr matching gain here fsr max is the most positive gain error of the adc. fsr min is the most negative gain error. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula : enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. noise free code resolution noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as fo llows: noise free code resolution = log 2 (2 n / peak - to - peak noise ) noise free code resolution is expressed in bits . effective resolution effective resolution is calculated as follows: effective resolution = log 2 (2 n / rms input noise ) effective resolution is expressed in bits . total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels ( db ) . dynamic range dynamic range is the ratio of the rms va lue of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels ( db ) . it is measured with a signal at ?60 dbf s to include all noise sources and dnl artifacts. signal -to - noise rati o (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels ( db ) . signal -to - (noise + distortion) (s inad) ratio sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels ( db ) . aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv x input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. rev. b | page 13 of 28
AD7903 data sheet rev. b | page 14 of 28 theory of operation figure 31. adc simplified schematic circuit information the AD7903 is a fast, low power, precise, dual 16-bit adc using a successive approximation architecture. the AD7903 is capable of simultaneously converting 1,000,000 samples per second (1 msps) and powers down between con- versions. when operating at 10 ksps, for example, it typically consumes 70 w per adc, making it ideal for battery-powered applications. the AD7903 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multichannel multiplexed applications. the AD7903 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 20-lead qsop that allows flexible configurations. the device is pin-for-pin compatible with the pseudo differential, 16-bit ad7902. converter operation the AD7903 is a dual successive approximation adc based on a charge redistribution dac. figure 31 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase of each adc, terminals of the array tied to the input of the comparator are connected to gnd via swx+ and swx?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the inx+ and inx? inputs. when the acquisition phase is complete and the cnvx input goes high, a conversion phase is initiated. when the conversion phase begins, swx+ and swx? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inx+ and inx? inputs, captured at the end of the acquisition phase, is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and refx, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /65,536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the AD7903 has an on-board conversion clock, the serial clock, sckx, is not required for the conversion process. transfer functions the ideal transfer characteristic for the AD7903 is shown in figure 32 and table 7. figure 32. adc ideal transfer function table 7. output codes and ideal input voltages description analog input, v ref = 5 v digital output code (hex) fsr ? 1 lsb +4.999962 v 0x7fff 1 midscale + 1 lsb +38.15 v 0x0001 midscale 0 v 0x0000 midscale ? 1 lsb ?38.15 v 0xffff ?fsr + 1 lsb ?4.999962 v 0x8001 ?fsr ?5 v 0x8000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). comp switches control busy output code cnvx control logic swx+ lsb swx? lsb inx+ refx gnd inx? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c 11755-011 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 11755-112
data sheet AD7903 rev. b | page 15 of 28 typical connection diagram figure 35 shows an example of the recommended connection diagram for the AD7903 when multiple supplies are available. analog inputs figure 33 shows an equivalent circuit of the input structure of the AD7903. the two diodes, d1 and d2, provide esd protection for the analog inputs, inx+ and inx?. the analog input signal must never exceed the reference input voltage (v ref ) by more than 0.3 v. if the analog input signal exceeds this level, the diodes become forward biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4841-1 in figure 35) are different from those of the v ref , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. figure 33. equivalent analog input circuit the analog input structure allows for the sampling of the differential signal between inx+ and inx?. by using these differential inputs, signals common to both inputs, and within the allowable common-mode input range, are rejected. figure 34. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (inx+ or inx?) can be modeled as a parallel combination of the c pin capacitor and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, where the switches are closed, the input impedance is limited to c pin . r in and c in make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the AD7903 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. figure 35. typical application diagram with multiple supplies c pin refx r in c in d1 d2 inx+ or inx? gnd 11755-114 90 85 80 75 70 65 60 1k 10k 100k 1m 10m frequency (hz) cmrr (db) 11755-040 AD7903 adcx 3-wire interface 2.5v v+ 1.8v to 5v 100nf 10f 2 100nf refx inx+ inx? vddx viox sdix cnvx sckx sdox gnd ref 1 20 ? v+ v? 0v to v ref 2.7nf 4 20 ? v+ v? v ref to 0v ada4841-1 3 2.7nf 4 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see recommended layout in figure 54. 3 see the driver amplifier choice section. 4 optional filter. see the analog inputs section. 11755-013
AD7903 data sheet driver amplifier cho ice although the AD7903 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noi se performance of the AD7903 . the noise from the driver is filtered by the one - pole, low - pass filter of the AD7903 analog input circuit , made by r in and c in or by the external filter, if one is used. because the typical noise of the AD7903 is 40 v rms , the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 40 40 log 20 n 3db loss ne f snr here f ? 3db is the input bandwidth, in megahertz, of the AD7903 (10 mhz) or the cutoff fre quency of the input filter, if one is used. n is the noise gain of the amplifier ( for example, gain = 1 in buffer configuration ; see figure 35) . e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver must have a thd perfor mance that is commensurate with the AD7903 . ? for multichannel , multiplexed applications, the driver amplifier and the AD7903 analog input circuit must settle for a full - scale step onto the capacitor array at a 16 - bit level (0.00 15%, 15 ppm). in the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a 16 - bit level . be sure to verify the settling time prior to driver selection . table 8 . recommended driver amplifiers amplifier typical application ada4941 -1 very low noise, low power, single to differential ada4841 -x very low noise, small, and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8655 5 v single supply, low noise ad8605 , ad8615 5 v single supply, low pow er single - to - differential driver for applications using a single - ended analog signal, either bipolar or unipolar, the ada4941 - 1 single - ended - to - differential driver allows a differential input to the device . the schematic is shown in figure 36. r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ) . r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. for example, for the 10 v range with a 4 k? impedance, r1 = 4 k? and r2 = 1 k?. r3 and r4 set the common mode on the in x ? input, and r5 and r6 set the common mode on the inx+ input of the adc. the common mode must be close to v ref /2. for example, for the 10 v range with a single supply, r3 = 8.45 k?, r4 = 11.8 k?, r5 = 10.5 k?, and r6 = 9.76 k?. figure 36 . single - ended - to- differential driver circuit 20? 20? 10f r1 100nf +2.5v +5v ref +5.2v ?0.2v c f r2 r4 r6 10v, 5v, .. r3 r5 refx vddx gnd inx+ inx? AD7903 adcx 2.7nf 2.7nf ada4941-1 in fb outp outn ref 100nf 1 1755- 1 15 rev. b | page 16 of 28
data sheet AD7903 voltage reference in put the AD7903 voltage reference input, ref, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the ref x and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605 ), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chi p capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference decoupling capacitor with values as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref x and gnd pins. power supply the AD7903 uses two power supply pins per adc : a core supply ( vdd x ) and a digital input/output interface supply ( vio x ) . vio x allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio x and vdd x can be tied together. the AD7903 is independent of power supply sequencing between vio x and vdd x . additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 37. figure 37 . psrr vs. frequency the AD7903 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this makes the part ideal for low sampling rates (of even a few hertz) and low battery - powered applications. figure 38 . operating currents per adc vs. sampling rate d igital interface although the AD7903 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the AD7903 is compatible with spi, qspi, digital hosts, and dsps. in this mode, the AD7903 can use either a 3 - wire or 4 - wire interface. a 3 - wire interface using the cnv x , s ck x , and sdo x signals minimizes wiring connections useful, for instance, in isolated applications. a 4 - wire interface using the sdi x , cnv x , sck x , and sdo x signals allows cnv x , which initiates the conversions, to be independent of the readback timing (sdi x ). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the AD7903 provides a daisy - chain feature using the sdi x input for cascading multiple adcs on a single data line similar to a shift register. with the AD7903 housing two adcs in one package, chain mode can be utilized to acquire data from both adcs while using only one set of 4 - wire user int erface signals. the mode in which the device operates depends on the sdi x level when the cnv x rising edge occurs. cs mode is selected if sdi x is high, and chain mode is selected if sdi x is low. the sdi x hold time is such that when s di x and cnv x are connected to gether, chain mode is always selected. in either mode, the AD7903 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data read ing . otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled as follows: ? in cs mode if cnv x or sdi x is low when the adc conversion ends (see figure 42 and figure 46). ? in chain mode if sck x is high during the cnv x rising edge (see figure 50). 95 90 85 80 75 70 65 60 psrr (db) 1k 10k 100k 1m frequency (hz) 11755-139 10 1 0.1 0.01 0.001 operating currents (ma) 100000 sampling rate (sps) 10000 1000000 i ref 11755-137 i vdd i vio rev. b | page 17 of 28
AD7903 data sheet rev. b | page 18 of 28 cs mode cs mode, 3-wire interface without busy indicator cs mode, using a 3-wire interface without a busy indicator, is usually used when a single AD7903 is connected to a spi- compatible digital host. the connection diagram is shown in figure 39, and the corresponding timing diagram is shown in figure 40. with sdix tied to viox, a rising edge on cnvx initiates a conversion, selects cs mode, and forces sdox to high impedance. when a conversion is initiated, it continues until completion, irrespective of the state of cnvx. this can be useful, for instance, to bring cnvx low to select other spi devices, such as analog multiplexers. however, to avoid generation of the busy signal indicator, cnvx must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. when the conversion is complete, the AD7903 enters the acquisition phase and powers down. when cnvx goes low, the msb is automatically output onto sdox. the remaining data bits are clocked by subsequent sckx falling edges. the data is valid on both sckx edges. although the rising edge can be used to capture the data, a digital host using the falling edge of sckx allows a faster reading rate, provided that it has an acceptable hold time. after the 16 th sckx falling edge or when cnvx goes high (whichever occurs first), sdox returns to high impedance. figure 39. cs mode, 3-wire interface without busy indicator connection diagram (sdix high) figure 40. cs mode, 3-wire interface without busy indi cator serial interface timing (sdi high) AD7903 sdix sdox cnvx sckx convert data in clk digital host viox 11755-116 sdix = 1 t cnvh t conv t cyc cnvx acquisition acquisition t acq t sck t sckl conversion sckx t en t hsdo 123 14 1516 t dsdo t dis t sckh sdox d15 d14 d13 d1 d0 11755-216
data sheet AD7903 rev. b | page 19 of 28 cs mode, 3-wire interface with busy indicator cs mode, using a 3-wire interface with a busy indicator, is usually used when a single AD7903 is connected to an spi- compatible digital host having an interrupt input. the connection diagram is shown in figure 41, and the corresponding timing is shown in figure 42. with sdix tied to viox, a rising edge on cnvx initiates a conversion, selects cs mode, and forces sdox to high impedance. sdox is maintained in high impedance until the completion of the conversion, irrespective of the state of cnvx. prior to the minimum conversion time, cnvx can be used to select other spi devices, such as analog multiplexers, but cnvx must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdox line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the AD7903 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sckx falling edges. the data is valid on both sckx edges. although the rising edge can be used to capture the data, a digital host using the sckx falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the optional 17 th sckx falling edge or when cnvx goes high (whichever occurs first), sdox returns to high impedance. if multiple adcs are selected at the same time, the sdox output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. figure 41. cs mode, 3-wire interface with busy indicator connection diagram (sdix high) figure 42. cs mode, 3-wire interface with busy indicator serial interface timing (sdix high) AD7903 sdix sdox cnvx sckx convert data in clk digital host viox irq viox 47k? 11755-118 t conv t cnvh t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sckx cnvx sdix = 1 sdox d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis 11755-218
AD7903 data sheet rev. b | page 20 of 28 cs mode, 4-wire interface without busy indicator cs mode, using a 4-wire interface without a busy indicator, is usually used when both adcs within the AD7903 are connected to a spi-compatible digital host. see figure 43 for an AD7903 connection diagram example. the corresponding timing diagram is shown in figure 44. with sdix high, a rising edge on cnvx initiates a conversion, selects cs mode, and forces sdox to high impedance. in this mode, cnvx must be held high during the conversion phase and the subsequent data readback. (if sdix and cnvx are low, sdox is driven low.) prior to the minimum conversion time, sdix can be used to select other spi devices, such as analog multiplexers, but sdix must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the AD7903 enters the acquisition phase and powers down. each adc result can be read by bringing its respective sdix input low, which consequently outputs the msb onto sdox. the remaining data bits are then clocked by subsequent sckx falling edges. the data is valid on both sckx edges. although the rising edge can be used to capture the data, a digital host using the sckx falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th sckx falling edge or when sdix goes high (whichever occurs first), sdox returns to high impedance, and another adc result can be read. figure 43. cs mode, 4-wire interface without busy indicator connection diagram figure 44. cs mode, 4-wire interface without busy indicator serial interface timing AD7903 adc2 sdi2 sdo2 cnv2 sck2 convert data in clk digital host cs1 cs2 AD7903 adc1 sdi1 sdo1 cnv1 sck1 11755-120 t conv t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sckx cnvx t ssdicnv t hsdicnv sdox d 1 15 d 1 13 d 1 14 d 1 1d 1 0d 2 15 d 2 14 d 2 1 d 2 0 t hsdo t en 1 2 3 14 1516 1718 30 3132 t dsdo t dis sdi1 (cs1) sdi2 (cs2) 11755-220
data sheet AD7903 rev. b | page 21 of 28 cs mode, 4-wire interface with busy indicator cs mode, using a 4-wire interface with a busy indicator, is usually used when an AD7903 is connected to a spi-compatible digital host with an interrupt input. this cs mode is also used when it is desirable to keep cnvx, which is used to sample the analog input, independent of the signal that is used to select the data reading. this independence is particularly important in applications where low jitter on cnvx is desired. the connection diagram is shown in figure 45, and the corresponding timing is given in figure 46. with sdix high, a rising edge on cnvx initiates a conversion, selects cs mode, and forces sdox to high impedance. in this mode, cnvx must be held high during the conversion phase and the subsequent data readback. (if sdix and cnvx are low, sdox is driven low.) prior to the minimum conversion time, sdix can be used to select other spi devices, such as analog multiplexers, but sdix must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdox goes from high impedance to low impedance. with a pull-up on the sdox line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the AD7903 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sckx falling edges. the data is valid on both sckx edges. although the rising edge can be used to capture the data, a digital host using the sckx falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the optional 17 th sckx falling edge or sdix going high (whichever occurs first), sdox returns to high impedance. figure 45. cs mode, 4-wire interface with busy indicator connection diagram figure 46. cs mode, 4-wire interface with busy indicator serial interface timing AD7903 sdix sdox cnvx sckx convert data in clk digital host irq viox 47k ? cs1 11755-122 t conv t cyc a cquisition t ssdicnv acquisition t acq t sck t sckh t sckl conversion sdix t hsdicnv sckx cnvx sdox t en d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis 11755-222
AD7903 data sheet rev. b | page 22 of 28 chain mode chain mode without busy indicator chain mode without a busy indicator can be used to daisy- chain both adcs within an AD7903 on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. see figure 47 for a connection diagram example using both adcs in an AD7903 . the corresponding timing is shown in figure 48. when sdix and cnvx are low, sdox is driven low. with sckx low, a rising edge on cnvx initiates a conversion, selects chain mode, and disables the busy indicator. in this mode, cnvx is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdox and the AD7903 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sckx falling edges. for each adc, sdix feeds the input of the internal shift register and is clocked by the sckx falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sckx edges. although the rising edge can be used to capture the data, a digital host using the sckx falling edge allows a faster reading rate and, consequently, more AD7903 devices in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 47. chain mode without busy indicator connection diagram figure 48. chain mode without busy indicator serial interface timing convert data in clk digital host AD7903 adc2 sdi2 sdo2 cnv2 sck2 AD7903 adc1 sdi1 sdo1 cnv1 sck1 11755-124 t conv t cyc t ssdisck t sckl t sck t hsdisck t acq acquisition t ssckcnv acquisition t sckh conversion sdo1 = sdi2 t hsckcnv sckx cnvx sdi1 = 0 sdo2 t en d 1 15 d 1 14 d 1 13 d 2 15 d 2 14 d 2 13 d 2 1d 2 0d 1 15 d 1 14 d 1 0 d 1 1 d 1 1d 1 0 t hsdo 1 2 3 151617 14 18 30 31 32 t dsdo 11755-224
data sheet AD7903 rev. b | page 23 of 28 chain mode with busy indicator chain mode with a busy indicator can also be used to daisy- chain both adcs within an AD7903 on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with limited interfacing capacity. data readback is analogous to clocking a shift register. see figure 49 for a connection diagram example using three AD7903 adcs. the corresponding timing is shown in figure 50. when sdix and cnvx are low, sdox is driven low. with sckx high, a rising edge on cnvx initiates a conversion, selects chain mode, and enables the busy indicator feature. in this mode, cnvx is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdox pin of the adc closest to the digital host (see the adc labeled adcx in the AD7903 b box in figure 49) is driven high. this transition on sdox can be used as a busy indicator to trigger the data readback controlled by the digital host. the AD7903 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sckx falling edges. for each adc, sdix feeds the input of the internal shift register and is clocked by the sckx falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sckx falling edge allows a faster reading rate and, consequently, more adcs in the chain, provided that the digital host has an acceptable hold time. figure 49. chain mode with bu sy indicator connection diagram figure 50. chain mode with busy indicator serial interface timing convert data in clk digital host AD7903 sdixb sdoxb cnvx sckx AD7903 AD7903 a AD7903 b sdi1a sdo1a cnvx sckx irq AD7903 sdi2a sdo2a cnvx adcx adc1 adc2 sckx 11755-126 notes 1. dashed line denoted adcs are within a given package. 2. sdi1a and sdo1a refer to the sdi1 and sdo1 pins in adc1 in the first AD7903 of the chain (AD7903 a). sdi2a and sdo2a refer to the sdi2 and sdo2 pins in adc2 of AD7903 a. likewise, sdixb and sdoxb refer to the sdix and sdox pins in both adc1 and adc2 of the second AD7903 in the chain (AD7903 b) t conv t cyc t ssdisck t sckh t sck t hsdisck t acq t dsdosdi t dsdosdi t dsdodsi acquisition t ssckcnv acquisition t sckl conversion t hsckcnv sckx cnvx = sdi1 a s do1 a =sdi2 a s do2 a =sdix b sdox b t en d a1 15 d a1 14 d a1 13 d a2 15 d a2 14 d a2 13 d bx 15 d bx 14 d bx 13 d a2 1d a2 0d a1 15 d a1 14 d a1 1d a1 0 d bx 1d bx 0d a2 15 d a2 14 d a1 0 d a1 1 d a2 0 d a2 1d a1 14 d a1 15 d a1 1d a1 0 t hsdo 123 151617 4 1819 3132333435 474849 t dsdo t dsdosdi t dsdosdi 11755-226
AD7903 data sheet application s information simultaneous s ampling by having two unique user interfaces, the AD7903 provides maximum flexibility with respect to how conversion results are accessed from the device. the AD7903 provides an option for the two user interfaces to share the convert start (cnv x ) signal from the digital host , creating a 2 - channel , simultaneous sampling device. in applications such as control applications, where latency between the sampling instant and the availability of results in the digital host is critical, it is recommended th at the AD7903 be configure d as shown in figure 51 . this configuration allows simultaneous data read s, in addi tion to simultaneous sampling. however, this configuration also require s an additional data input pin on the digital host. this scen ario allow s the fastest throughput because it requires only 15 or 16 sck x falling edges (depending on the status of the busy indicator ) to acquire data from the adc. alternatively, for applications where simultaneous sampling is require d but pins on the digital host are limi ted, the two user interfaces on the AD7903 can be connected in one of the daisy - chain configuration s s hown in figure 47 and figure 49 . this daisy chaining allow s the user to implement simultaneous sampling functionality while requiring only one digital host input pin. this scenario require s 31 or 32 sck x falling edges (depending on the status of the busy indicator) to acquire data from the adc . figure 51 shows a n example of a simultaneous sampling system using two data inputs for the digital host. the corresponding timing diagram in figure 52 shows a cs mode , 3 - w ire simul - taneous sampling serial interface with out a busy i ndicator. however, any of the 3 - wire or 4 - wire serial interface timing options can be used. figure 51 . potential simultaneous sampling connection diagram figure 52 . potential simultaneous sampling serial interface timing vio1 vio2 convert data in 2 clk digital host data in 1 AD7903 adc2 sdi2 sdo2 cnv2 sck2 AD7903 adc1 sdi1 sdo1 cnv1 sck1 11755-324 sdix = 1 t cnvh t conv t cyc cnvx acquisition acquisition t acq t sck t sckl conversion sckx t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh sdo1 d15 d14 d13 d1 d0 sdo2 d15 d14 d13 d1 d0 11755-316 rev. b | page 24 of 28
data sheet AD7903 functiona l saf et y considerations the AD7903 contains two physically isolated adcs, making it ideally suited for functional safety applications. because of this isolation, each adc features an independent user interface, an independent reference input, an independent analog input , and independent supplies. physical isolation renders the device suitable for taking verification/ back up measurements while sep arating the verification adc from the system under control. although the simultaneous sampling section describe s how to operate the device in a simultaneous nature, t he circuit is actually composed of two individual signal chains. this separation makes the AD7903 ideal for handling redundant measurement applications. implementing a signal chain with redundant adc mea surement can contribute to a no single error system. figure 53 shows a typical functional safety application circuit consisting of a redundant m easurement with the employment of monitoring the inverted signal. the inversion is applied to detect common cause failures where it is expected that the circuit output move s in the same direction during a fault condition , i nstead of moving in the opposite direc tion as expected. in addition , the qsop package that houses the device provides access to the leads for inspection . figure 53 . typical functional safety block diagram 11755-146 gnd vdd1 vdd2 2.5v ref1 ref2 ref = 2.5v to 5v adc1 in1+ in1? vio1 sdi1 sck1 cnv1 sdo1 sdi1 sck1 cnv1 sdo1 sdi2 vio1 vio2 sck2 cnv2 sdo2 adc2 in2+ in2? vio2 sdi2 sck2 cnv2 sdo2 AD7903 ref 10v, 5v, ... ada4941-1 ada4941-1 physically isolated adcs rev. b | page 25 of 28
AD7903 data sheet layout design t he printed circuit board (pcb) of the AD7903 such that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD7903 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto th e die unless a ground plane under the AD7903 is used as a shield. do not run f ast switching signals, such as cnv x or clocks, near analog signal paths. avoid c rossover of digital and analog signals. to avoid signal fidelity issues, take c are to ensure monotonicity of digital edges in the pcb layout . use a t least one ground plane . it can be shared between or split between the digital and analog sections. in the latter case, join the planes underneath the AD7903 . the AD7903 voltage reference input s, ref 1 and ref2, ha ve a dynamic input impedance . decouple these reference inputs with minimal parasitic inductances by placing the reference decoupling ceramic capacitor in close proximity to ( ideally , right up against ) the ref x and gnd pins and then connecting them with wide, low impedance traces. finally, decouple the power s upplies , vdd x and vio x , with ceram ic capacitors, typically 100 nf. place them in close proximity to the AD7903 and connect them using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. see figure 54 for a n example of layout fol lowing these rules . evaluating performance of the AD7903 other recommended layouts for the AD7903 are outlined in user guide ug - 609. t he package for the evaluation board ( e va l - AD7903 sdz ) includes a fully assembled and tested evaluation board, user guid e , and software for controlling the board from a pc via the e va l - sdp - cb1z . figure 54 . example layout of the AD7903 (top layer) 11755-147 ref1 vdd1 in1+ in1? gnd ref2 vdd2 in2+ in2? gnd vio1 sdi1 sck1 sdo1 cnv1 vio2 sdi2 sck2 sdo2 cnv2 gnd ref ref ref gnd gnd gnd vdd vdd gnd vio vio gnd rev. b | page 26 of 28
data sheet AD7903 rev. b | page 27 of 28 outline dimensions figure 55. 20-lead shrink small outline package [qsop] (rq-20) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option ordering quantity AD7903brqz ?40c to +125c 20-lead shrink sm all outline package (qsop) rq-20 tube, 56 AD7903brqz-rl7 ?40c to +125c 20-lead shrink small outline package (qsop) rq-20 reel, 1,000 eval-AD7903sdz evaluation board eval-sdp-cb1z controller board 1 z = rohs compliant part. compliant to jedec standards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 20 11 10 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 08-19-2008-a
AD7903 data sheet rev. b | page 28 of 28 notes ?2013C2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11755-0-8/14(b)

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